Analog Master Slice
The Analog Master Slice is the service which offers the original analog semi-customized IC/LSI for customers.The wafers which are prefabricated transistors, resistors, capacitors and other devices are prepared, then creation of the original IC/LSI is accomplished by adding the glass mask of wiring layers to be customized as desired.The cost and lead time can be reduced since the common master slice is utilized.
- General ICs such as OpAmps does not have enough functions
- Creation of IC/LSI from discrete circuit
- The cost and the lead time does not meet your requirement if utilizing full customized IC
This service can be helpful for the customers in case of situations listed above.
*We are also handling the foundry service which offering OEM wafer production.
Feature
High voltage, 5 inches, Bipolar is utilized.
The lead time for ES(engineering samples) is usually 4 to 6 weeks after the layout design is completed.
The basic flow of developing an Analog Master Slice is as follows.
Nisshinbo Micro Device's analog master slice is preparing the type of transistor array which combines integrated transistors, resistors, capacitors as well as individual devices. In addition two types of macro-cell which combines Nisshinbo Micro Device's standard Op Amps.Our customers are offered various options as shown above.Please refer to below for more detailed information.
Transistor Array Type
Transistor Array Type | TA-1-2-4 (Released) |
TA-1-1-3 (Prototype) |
TA-1-4-8 (Under Planning) |
---|---|---|---|
Wafer Process | High-Voltage 5inch Bipolar | ||
Maximum Supply Voltage | 43V | ||
Maximum Operating Voltage | 40V | ||
Operating Temperature Range | -40 to +125°C | ||
Number of Block | 8 | 3 | 32 |
Number of NPN BJT | 368 | 138 | 1472 |
Number of LPNP BJT | 352 | 132 | 1408 |
Number of LR-POL Resistor (one-element=125Ω) |
1840 | 714 | 7168 |
Number of HR-POL Resistor (one-element=5kΩ) |
1744 | 654 | 6976 |
Number of MOS Capacitor (one-element=5pF) |
16 | 6 | 64 |
Changeable Mask Layers for Interconnect |
3-Layers(AL,VIA,AL2) | ||
Package | LQFP48 | DIP16 SSOP20/24/32 |
COB |
Application | •Automotive;Body Control •Industrial;Sensor AFE(Analog Front End) |
Macrocell Type
Macrocell Type | MC-1-3-3 (To be Confirm) |
MC-1-1-0 (Under Planning) |
MC-1-4-4 (Under Planning) |
---|---|---|---|
Wafer Process | High-Voltage 5inch Bipolar | ||
Maximum Supply Voltage | 43V | ||
Maximum Operating Voltage | 40V | ||
Operating Temperature Range | -40 to +125°C | ||
Number of Opamp Cell | NJM2904 Type:3 NJM4558 Type:3 |
NJM2904 Type:1 NJM4558 Type:0 |
NJM2904 Type:4 NJM4558 Type:4 |
Number of NPN BJT | 12 | 4 | 20 |
Number of LPNP BJT | 12 | 4 | 20 |
Number of HR-POL Resistor (one-element=5kΩ) |
375 | 75 | 500 |
Number of HR-POL Resistor (one-element=10kΩ) |
72 | 12 | 96 |
Number of HR-POL Resistor (one-element=20kΩ) |
72 | 12 | 96 |
Number of HR-POL Resistor (one-element=40kΩ) |
72 | 12 | 96 |
Number of HR-POL Resistor (one-element=80kΩ) |
72 | 12 | 96 |
Number of MOS Capacitor (one-element=8pF) |
16 | 12 | 32 |
Changeable Mask Layers for Interconnect |
3-Layers(AL,VIA,AL2) | ||
Package | LQFP48 | DIP14/16 SSOP14/16 |
COB |
Application | •Audio;Pre-Amp •Consumer;Sensor AFE(Analog Front End) |
Circuit Diagram
Analog master slice in Nisshinbo Micro Device Co., offers the following process design kit(PDK).
- Design rule
- Schematic symbol
- SPICE model parameter
- Layout data
- DRC/LVS verification rule
Correspondence EDA tools
Cadence Design Systems, Inc. | ![]() |
|
---|---|---|
Schemaic | Virtuoso Schematic Editor | Gateway |
Circuit Simulator | Virtuoso Multi-Mode Simualtion | SmartSpice |
Layout | Virtuoso Layout Editor (GDS2 File) |
Expert (GDS2/Tech File) |
DRC/LVS | Dracula(*1) | Guardian(*2) |
- *1 Tapeout Signoff Verification
- *2 Interactive Verification
The brand name and the name of the company are the trademarks or registered trademarks of each company.
Guarantee item
- Analog Master Slices guarantee item is the following.
- PCM Guarantee
- Visual Inspection
- Automotive
Option services
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- Wafer Test
- Wafer Final Test
- Burn-in Test
Shipping
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- Wafer
*The PCM data is appended at delivery.
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