0.6µm CMOS Analog Mixed Mode
0.6µm CMOS Analog Mixed Mode
Process Outline
- 0.6µm P-Sub 1P3M(1-Poly and 3-Metal) Twin Well CMOS generic process.
- Maximum operational voltage is 6V and maximum rating is 6.5V.
- Transistor Characterizations are as follows;
| Device | Tr.type | Vth[V] *1 | Ids[uA/um] | Ioff[pA/um] |
|---|---|---|---|---|
| PMOS | Logic Tr. | -0.95 | 224 | 0.05 |
| Low Tr. | -0.60 | 160 | 0.3 | |
| Analog Tr. | -0.80 | 164 | 0.2 | |
| NMOS | Logic Tr. | 0.75 | 460 | 0.1 |
| Low Tr. | 0.35 | 296 | 30 | |
| Analog Tr. | 0.60 | 264 | 0.2 |
- *1 Extrapolated Threshold at Vd=0.1V
- Vth tunable to match customer's needs.
Option Modules
- Depletion Transistor.
- 20V and 40V Transistors.
- Vertical PNP and Lateral PNP Transistors.
- Triple well.
- 0.5k , 1k , 2k and 10k-ohm/sq High Resistivity Poly Resistor. (* Tunable high resistivity poly to match customer's needs.)
- Thin Film Resistor.
- Low temperature coefficient Poly Resistor.
- Double Poly Capacitor (PiP).
- Laser Trimming Fuse.
Design Environment
- BSIM3V3 based on analog oriented extraction is used for SPICE simulation.
- SPICE parameters are ready for HSPICE, SPECTRE and Smart SPICE.
- Characterization report is available.
- Logic libraries and I/O libraries are available.
- ESD protection circuit is available.